A metal line comprises a lattice of metal ions and non-localized free electrons. The metal ions are formed from metal atoms that donate some of their electrons to a common conduction band of the lattice, and the non-localized free electrons move with relatively small resistance within the lattice under an electric field. Normal metal lines, excluding superconducting materials at or below a superconducting temperature, have finite conductivity, which is caused by interaction of electrons with crystalline imperfections and phonons which are thermally induced lattice vibrations.
When electrical current flows in the metal line, the metal ions are subjected to an electrostatic force due to the charge of the metal ion and the electric field to which the metal ion is exposed to. Further, as electrons scatter off the lattice during conduction of electrical current, the electrons transfer momentum to the metal ions in the lattice of the conductor material. The direction of the electrostatic force is in the direction of the electric field, i.e., in the direction of the current, and the direction of the force due to the momentum transfer of the electrons is in the direction of the flow of the electrons, i.e., in the opposite direction of the current. However, the force due to the momentum transfer of the electrons is generally greater than the electrostatic force. Thus, metal ions are subjected to a net force in the opposite direction of the current, or in the direction of the flow of the electrons.
High defect density, i.e., smaller grain size of the metal, or high temperature typically increases electron scattering, and consequently, the amount of momentum transfer from the electrons to the conductor material. Such momentum transfer, if performed sufficiently cumulatively, may cause the metal ions to dislodge from the lattice and move physically. The mass transport caused by the electrical current, or the movement of the conductive material due to electrical current, is termed electromigration in the art.
In applications where high direct current densities are used, such as in metal interconnects of semiconductor devices, electromigration causes a void in a metal line or in a metal via. Such a void results in a locally increased resistance in the metal interconnect, or even an outright circuit “open.” In this case, the metal line or the metal via no longer provides a conductive path in the metal interconnect. Formation of voids in the metal line or the metal via can thus result in a product failure in semiconductor devices.
FIGS. 1A and 1B show an exemplary prior art metal interconnect structure comprising a lower level metal interconnect structure 3′ and an upper level metal interconnect structure 6′. FIG. 1A is a vertical cross-sectional view of the exemplary prior art metal interconnect structure, and FIG. 1B is a modified top-down view in which an upper dielectric material layer 40 and an optional dielectric cap layer 42 are removed from a top-down view for clarity.
The lower level metal interconnect structure 3′ comprises a lower dielectric material layer 10 embedding a lower conductive structure, which includes a lower metallic liner 20 and a line-level metal portion 30. The lower metallic liner 20 and the line-level metal portion 30 collective form at least a metal line. Depending on whether a dual damascene integration scheme is employed or a single damascene integration scheme is employed to form the lower level metal interconnect structure 3′, the lower metallic liner 20 and the line-level metal portion 30 may constitute the metal line and at least one integrated via extending downward, or may constitute only the metal line without any via extending downward. The lower metallic liner 20 is formed on recessed surfaces of the lower dielectric material layer 10, i.e., surfaces below the level of the interface between the lower dielectric material layer 10 and the upper level metal interconnect structure 6′. The line-level metal portion 30 comprises a metal such as copper, and is formed directly on, and the inside of, the lower metallic liner 20. The top surfaces of the lower metallic liner 20 and the line-level metal portion 30 are substantially coplanar with the top surface of the lower dielectric material layer 10, i.e., the interface between the lower level metal interconnect structure 3′ and the upper level metal interconnect structure 6′ is substantially planar and level without any protrusions. Such geometry results from interlevel planarization process that is routinely used in semiconductor manufacturing.
The upper level metal interconnect structure 6′ comprises the upper dielectric material layer 40 and the optional dielectric cap layer 42 embedding an upper conductive structure, which includes an upper metallic liner 50 and a via-level metal portion 60. The upper metallic liner 50 and the via-level metal portion 60 collective form at least a conductive via. Depending on whether a dual damascene integration scheme is employed or a single damascene integration scheme is employed to form the upper level metal interconnect structure 6′, the upper metallic liner 50 and the via-level metal portion 60 may constitute the conductive via and a metal line integrally formed with the conductive via 60, or may constitute only the conductive via without any integrally formed metal line. The upper metallic liner 50 is formed on recessed surfaces of the upper dielectric material layer 50, i.e., surfaces below the topmost surface of the upper level metal interconnect structure 6′. The via-level metal portion 60 comprises a metal such as copper, and is formed directly on, and inside of, the upper metallic liner 60.
A salient feature of the exemplary prior art metal interconnect structure is that the entirety of the interface between the conductive via (50, 60) and the metal line (20, 30) consists of a contact between the upper metallic liner 50 and the line-level metal portion 30. The upper metallic liner 50 does not abut the lower dielectric material layer 10. Further, the layout of the conductive via (50, 60) and the metal line (20, 30) is designed to avoid direct contact between the upper metallic liner 50 and the lower metallic liner 20. This is often effected by providing enough distance, i.e., a distance that exceeds lithographic overlay variations, between the projected location of the perimeter of the upper metallic liner 50 and projected location of the perimeter of the lower metallic liner 20. The primary purpose of such designs employed for the exemplary prior art metal interconnect structure is to maximize the contact area between the upper metallic liner 50 and the line-level metal portion 30 so that the resistance at the interface between the conductive via (50, 60) and the metal line (20, 30) is minimized, thereby suppressing temperature elevation during usage and preventing electromigration, which accelerates at elevated temperatures.
FIG. 2 is a graph showing data for resistance shift in time for a group of physical interconnect structures manufactured and tested during the course of research leading to the present invention by employing the exemplary prior art metal interconnect structure of FIGS. 1A and 1B. For this test, a copper line having a width of about 0.4 micron was subjected to a current density of about 25 mA/μm2 at the interface between a conductive via (50, 60; See FIGS. 1A and 1B) and a metal line (20, 30: See FIGS. 1A and 1B) at an elevated temperature of 300° C. The resistance of each physical interconnect structure was monitored and plotted as a function of time in FIG. 2, which shows clustered failures around 25 hours. The resistance of the physical interconnect structures increase abruptly around 25 hours with electromigration failure as voids form at the interface between the conductive via (50, 60) and the metal line (20, 30).
In view of the above, there exists a need to provide a metal interconnect structure between a metal line and a conductive via that provides enhanced electromigration resistance, and methods of providing the same.